1. Field of the Invention
The present invention generally relates to methods of fabricating devices on semiconductor substrates. More specifically, the present invention relates to a method of fabricating a tunneling nanotube field effect transistor on a semiconductor substrate.
2. Description of the Related Art
Microelectronic devices are generally fabricated on semiconductor substrates as integrated circuits. A complementary metal-oxide-semiconductor (CMOS) field effect transistor is one of the core elements of the integrated circuits. Dimensions and operating voltages of CMOS transistors are continuously reduced, or scaled down, to obtain ever-higher performance and packaging density of the integrated circuits. In particular, the threshold voltage Vth (i.e., voltage that is necessary to turn a transistor ON) is reduced in such transistors.
Switching characteristics of a CMOS transistor may be described by a parameter known in the art as an inverse sub-threshold slope that measures the gate voltage required to change the current through the device by one order of magnitude. In conventional CMOS transistors, the inverse sub-threshold slope is about 60 mV/decade and for decreasing threshold voltages Vth the difference between output currents in the ON and OFF state of the transistor decreases. Too small ON/OFF current ratios prevent proper operation of digital circuits that comprise such transistors and are considered one of the major challenges in ultimately scaled devices.
Therefore, there is a need in the art for an improved method of fabricating a field effect transistor.